The present invention relates to an electronic device, for example, one configured with an LPDDR4 (low power double data rate 4) SDRAM (synchronous DRAM) and a controller therefor both included in a SiP (system in package).
In Japanese Translation of PCT International Application Publication No. 2011-513845, for example, a dual-channel memory architecture is disclosed which is configured with a first memory device and a second memory device. The first memory device is coupled to a memory controller using a common address bus and a first clock signal. The second memory device is coupled to a memory controller using a common address bus and a second clock signal. The polarity of the second clock signal is a reversal of the polarity of the first clock signal. JEDEC Standard JESD209-4 includes the LPDDR4 standard.